The invention relates to a semiconductor technology, and more particularly, to a method of fabricating a semiconductor device by electron beam annealing.
In semiconductor fabrication, interconnect structures are typically formed in the back end of line (BEOL) to connect a plurality of electric devices. As integrated circuits (ICs) are scaled down to deep submicron regime, RC delay becomes increasingly dominant over intrinsic gate delay. To solve this issue, two realistic methods are popularly accepted. One is the use of copper as the conductor for multilevel interconnects to decrease the resistance parts of RC delay. Another is the use of a low dielectric constant material to reduce coupling capacitance between metal lines.
In a conventional semiconductor device fabrication process, the interconnect structure is annealed by a thermal process to reduce a resistance of the interconnect structure. Normally, the thermal annealing process must be carried out at relatively high temperatures, such as 800 to 1200° C., leading to a serious impact on other portions of the semiconductor devices. For example, some dopants may diffuse because of a concentration gradient during the high temperature annealing process, seriously deteriorating electric performance of the semiconductor devices. In addition, the interconnect structure may not be well annealed, particularly tinny conductive lines. Additionally, the annealing efficiency varies with different dimensions.
Thus, a method of fabricating a semiconductor device with a reduced thermal process is desirable.